A compute fabric that removes 90% of the energy bill.

Move math into hardware. Use substrates whose physics performs the operations natively. Build one stack from chip to compiler. The energy reduction follows.

Reduce compute energy by 90% by 2030.

The goal is anchored in OpenIE’s Delaware Public Benefit Corporation charter. The IEA projects global datacenter electricity demand at 945 TWh by 2030 — more than Japan’s national consumption today.

A reduction of this size cannot be reached by incremental optimization of existing substrates. It requires changes to what compute does in hardware, to which substrates host the operations, and to the software stack that orchestrates them.

Three engineering decisions.

The ThermoEdge Compute Fabric is described by three first-principles decisions. Each addresses one segment of the energy bill. Together they require a Unified Design Architecture — UDA — because a fabric this integrated cannot be assembled out of separately-sourced layers.

01

Move more math into hardware.

Mathematical primitives that today run only in software are implemented as dedicated silicon. The historical pattern — FFT, DSP, dense linear algebra, video codecs — produced one to three orders of magnitude in energy reduction per operation when each crossed from software emulation to native silicon. The Periodic Stack of Computation identifies the 229 primitives that have not yet crossed.

Addresses · the software-emulation tax on every operation

02

Use energy-optimized substrates for that hardware.

Each substrate column hosts the operations its physics performs natively. The substrate physics provides the win — not the process node. The architecture absorbs the node disadvantage by reducing the operation count for every workload class. Mature, low-cost nodes are sufficient.

Addresses · the impedance mismatch between operation and substrate

03

Build the fabric as one stack with the hardware at the bottom.

A hardware abstraction layer, an operating system, a programming interface, a language, and a compiler are co-designed with the silicon. The energy reduction is delivered by the stack as a whole. The compiler dispatches operations across substrates by measured joule cost, using the JLandauer simulator as the cost surface.

Addresses · the gap between heterogeneous silicon and reachable software

Five substrates. One chip in the field.

Each substrate column hosts the class of operations whose physics performs it natively — the win comes from the substrate, not the process node. TESilicon is ThermoEdge's first shipping chip; the substrate archetypes drive the roadmap behind it.

TEPhotonics

130 nm SOI · 22 nm TFLN

Physics

MZI mesh + thin-film lithium niobate

Natural for

linear algebra · Fourier work

A native photonic MAC at 130 nm outperforms an emulated MAC on advanced digital silicon by orders of magnitude in joules per operation. Programmable hexagonal photonic meshes have shipped commercially with measured 0.28 dB/gate loss and 31 GHz free spectral range. Thin-film lithium niobate modulators at 100–200 GHz are commercially available at multiple foundries.

TEStochastic

22 nm eMRAM · 22 nm CMOS

Physics

sMTJ + CMOS thermal-noise

Natural for

sampling · Bayesian inference · MCMC

Stochastic-magnetic-tunnel-junction and CMOS-thermal-noise substrates produce calibrated randomness at the device level. A native sample on 22 nm sMTJ outperforms a softmax on advanced digital silicon. The substrate emits the probability distribution directly; the digital pipeline reads it without inventing it.

TEReversible

22 nm planar

Physics

LC-resonator-clocked adiabatic CMOS

Natural for

deterministic logic with energy recovery

Reversible logic sidesteps the Landauer floor by not erasing information at every gate. Adiabatic CMOS recovers a fraction of the switching energy on each cycle through resonant clocking. Test silicon at 22 nm has measured energy-recovery ratios of 1.77, with commercial systems publishing 50% recovery on real workloads.

TENeuromorphic

22 nm RRAM · Intel 4 / 28 nm spiking

Physics

in-memory crossbar · memristor · RRAM · PCM · MRAM

Natural for

event-driven processing · matrix-vector multiplication

Event-driven processors compute only when input arrives, eliminating the always-on tax of synchronous architectures. In-memory crossbars perform matrix-vector products at the storage cell, removing the data movement that dominates the digital energy bill. RRAM, PCM, and MRAM substrates are in commercial production at 22 nm.

TEQuantum

photonic-PIC · trapped-ion

Physics

photonic interferometers · trapped ion

Natural for

optimization · sampling on hard distributions

Quantum-photonic interferometers solve Ising-model optimization problems at speeds competitive with classical processors at room temperature. The substrate handles the narrow class of workloads where a quantum advantage exists in published silicon, and routes everything else to the substrate the physics suits.

TESilicon

22 nm · 4 form factors

First shipping chip

Architecture

heterogeneous RISC-V system on module

Natural for

always-on edge · field deployment · physical AI

ThermoEdge's first shipping chip. A heterogeneous RISC-V die that pairs application and real-time cores with processing-in-memory, on-die NVM, integrated radios, post-quantum security, and on-die energy harvesting. Four form factors share the same toolchain. TESilicon is not the fabric — it is one chip in it, designed to put always-on, energy-budgeted compute into the field where today's silicon will not go.

tesilicon.thermoedge.ai →

Math is the reference standard.
AI is one customer.

The compute fabric is not an AI accelerator. The customer surface is every workload class that does math.

The fabric routes each mathematical primitive to the substrate whose physics performs it natively.

Every workload class is mathematics.

Every customer class uses a different subset of mathematical primitives. The fabric is workload-neutral. The cost surface decides which substrate runs which primitive.

Scientific computing

PDE solvers, climate modeling, adjoint methods, numerical linear algebra.

Computational chemistry

Density functional theory, molecular dynamics, quantum chemistry methods.

Structural analysis

Finite-element analysis, modal decomposition, signal-subspace estimation.

Bayesian inference

MCMC, HMC, Langevin dynamics, probabilistic graphical models.

Cryptography

Modular arithmetic, lattice operations, formal protocol verification.

Genomic assembly

Sequence alignment, variant calling, de novo assembly graphs.

Real-time control

Robotics, signal processing, model-predictive control, sensor fusion.

AI / machine learning

Inference, training, retrieval, sampled generation. One customer among many.

The catalog and the cost surface.

Two OpenIE-published assets are operational today and load-bearing for the ThermoEdge architecture.

ThermoEdge is the hardware arm of OpenIE.

Thermodynamic Edge Intelligence Corp. is a subsidiary of Open Interface Engineering, Inc. — a Delaware Public Benefit Corporation. JoulesPerBit, Inc. is a sister subsidiary, shipping the joule-priced cloud software stack today.

The compute fabric is the data-tract instantiation of OpenIE’s published framework, the Periodic Stack of Computation. ThermoEdge builds the silicon and the orchestration that turn the Stack into a physical executor of mathematics.

The unit of sale is the artifact's lifetime, not the refresh cycle. Make once, use forever, return the substrate. The customer pays the second law — chip to invoice, in joules.