The fabric
A heterogeneous-substrate compute architecture engineered to reduce energy use by 90%. Five substrate variants. One co-designed stack from chip to compiler.
The compute fabric stack
The decisions
Mathematical primitives that today run only in software are implemented as dedicated silicon. The historical pattern — FFT, DSP, dense linear algebra, video codecs — produced one to three orders of magnitude in energy reduction per operation when each crossed from software emulation to native silicon. The Periodic Stack of Computation identifies the 229 primitives that have not yet crossed.
Addresses · the software-emulation tax on every operation
Each substrate column hosts the operations its physics performs natively. The substrate physics provides the win — not the process node. The architecture absorbs the node disadvantage by reducing the operation count for every workload class. Mature, low-cost nodes are sufficient.
Addresses · the impedance mismatch between operation and substrate
A hardware abstraction layer, an operating system, a programming interface, a language, and a compiler are co-designed with the silicon. The energy reduction is delivered by the stack as a whole. The compiler dispatches operations across substrates by measured joule cost, using the JLandauer simulator as the cost surface.
Addresses · the gap between heterogeneous silicon and reachable software
The substrates
Each substrate column targets the most mature, most available, lowest-cost foundry node on which its substrate is in commercial production. The architecture absorbs the node disadvantage by reducing the operation count for every workload class.
Photonic
Node
130 nm SOI · 22 nm TFLN
Physics
MZI mesh + thin-film lithium niobate
Natural for
linear algebra · Fourier work
A native photonic MAC at 130 nm outperforms an emulated MAC on advanced digital silicon by orders of magnitude in joules per operation. Programmable hexagonal photonic meshes have shipped commercially with measured 0.28 dB/gate loss and 31 GHz free spectral range. Thin-film lithium niobate modulators at 100–200 GHz are commercially available at multiple foundries.
Stochastic
Node
22 nm eMRAM · 22 nm CMOS
Physics
sMTJ + CMOS thermal-noise
Natural for
sampling · Bayesian inference · MCMC
Stochastic-magnetic-tunnel-junction and CMOS-thermal-noise substrates produce calibrated randomness at the device level. A native sample on 22 nm sMTJ outperforms a softmax on advanced digital silicon. The substrate emits the probability distribution directly; the digital pipeline reads it without inventing it.
Reversible
Node
22 nm planar
Physics
LC-resonator-clocked adiabatic CMOS
Natural for
deterministic logic with energy recovery
Reversible logic sidesteps the Landauer floor by not erasing information at every gate. Adiabatic CMOS recovers a fraction of the switching energy on each cycle through resonant clocking. Test silicon at 22 nm has measured energy-recovery ratios of 1.77, with commercial systems publishing 50% recovery on real workloads.
Neuromorphic
Node
22 nm RRAM · Intel 4 / 28 nm spiking
Physics
in-memory crossbar · memristor · RRAM · PCM · MRAM
Natural for
event-driven processing · matrix-vector multiplication
Event-driven processors compute only when input arrives, eliminating the always-on tax of synchronous architectures. In-memory crossbars perform matrix-vector products at the storage cell, removing the data movement that dominates the digital energy bill. RRAM, PCM, and MRAM substrates are in commercial production at 22 nm.
Quantum
Node
photonic-PIC · trapped-ion
Physics
photonic interferometers · trapped ion
Natural for
optimization · sampling on hard distributions
Quantum-photonic interferometers solve Ising-model optimization problems at speeds competitive with classical processors at room temperature. The substrate handles the narrow class of workloads where a quantum advantage exists in published silicon, and routes everything else to the substrate the physics suits.
Silicon SoM
Node
22 nm · 4 form factors
Physics
heterogeneous RISC-V system on module
Natural for
always-on edge · field deployment · physical AI
ThermoEdge's first shipping chip. A heterogeneous RISC-V die that pairs application and real-time cores with processing-in-memory, on-die NVM, integrated radios, post-quantum security, and on-die energy harvesting. Four form factors share the same toolchain. TESilicon is not the fabric — it is one chip in it, designed to put always-on, energy-budgeted compute into the field where today's silicon will not go.
Defensibility
Each substrate the fabric integrates is the subject of dozens of academic papers and several commercial products. The substrates are not the moat. The heterogeneous orchestration above them is.
The Periodic Stack of Computation. Published framework classifying every primitive operation in compute — 258 primitives across 33 families in 6 axes. The map the dispatch is built on.
The JLandauer simulator. Live operational software. The workload-evaluation tool partners use before silicon.
The joule receipt contract. Cost surface shared with sibling company JoulesPerBit. End-to-end joule-priced compute from chip to invoice across the OpenIE family — the customer pays the second law, not a markup over it.
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